3.4 NAND Flash Specific Header

After sending the reset and initialization commands, the ROM code reads the first page without internal PMECC and PMERRLOC enabled to determine whether the NAND Flash device parameters header is present. For redundancy, the header is made of 52 times the same 32-bit word. This 32-bit word must contain the NAND and PMECC parameters used in order to correctly read the remainder of the data in the NAND Flash device. For further details, refer to the relevant product data sheet (see Reference Documents).

If the header is not valid but the internal PMECC use is enabled, the NAND Flash device parameters and ECC correction parameters are inferred from the ONFI 2.2 parameters.

Important: Make sure the error detection and correction mechanisms are not activated at the same time. Failing to do so will provide unpredictable results.

To enable proper image loading and execution, the SAM9X60 and SAM9X7 ROM code relies on a specific NAND Flash header format. See PMECC Configuration Parameters for a brief overview of the key fields within this header and their roles during the initial boot process.

Figure 3-2. NAND Flash Specific Header Fields

For details about the fields, check the SAM9X60 and SAM9X7 Series data sheets (see Reference Documents).

Note: The eccOffset value is expressed in bytes and cannot be less than 2, as the first two bytes are usually reserved for bad block marking. Also, eccOffset and spareSize should be in a valid relation, which means that the eccOffset value plus the number of ECC bits should be higher than spareSize.

After configuring the internal PMECC peripheral, the ROM code re-reads the first page. During this second read, the PMECC can be enabled or not, depending on the PMECC usage configuration. The ROM code then checks for valid executable code located immediately after the header offset at 0xD0. If valid code is found, it is copied to the beginning of the internal SRAM, and execution is transferred to it.