38.8.3 USB Quality Of Service
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | QOSCTRL |
| Offset: | 0x03 |
| Reset: | 0x0F |
| Property: | PAC Write-Protection |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| DQOS[1:0] | CQOS[1:0] | ||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 1 | 1 | 1 | 1 | |||||
Bits 3:2 – DQOS[1:0] Data Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write data operation. Refer to SRAM Quality of Service.
Bits 1:0 – CQOS[1:0] Configuration Quality of Service
These bits define the memory priority access during the endpoint or pipe read/write configuration operation. Refer to SRAM Quality of Service.