38.1 Endpoint Bank, Address of Data Buffer
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | ADDR - Device |
| Offset: | 0x00 + evice*0x04 [evice=0..1] |
| Reset: | 0xxxxxxxx |
| Property: | NA |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| ADDR[31:24] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| ADDR[23:16] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| ADDR[15:8] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | x | x | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ADDR[7:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | R/W | |
| Reset | x | x | x | x | x | x | x | x | |
Bits 31:0 – ADDR[31:0] Data Pointer Address Value
These bits define the data pointer address as an absolute word address in RAM. The two least significant bits must be zero to ensure the start address is 32-bit aligned.