38.4 Enpoint Bank, Status of Bank
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | STATUS_BK |
| Offset: | 0x0A + n*0x0A [n=0..1] |
| Reset: | 0xxxxxxxx |
| Property: | NA |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| ERRORFLOW | CRCERR | ||||||||
| Access | R/W | R/W | |||||||
| Reset | x | x |
Bit 1 – ERRORFLOW Error Flow Status
This bit defines the Error Flow Status.
This bit is set when a Error Flow has been detected during transfer from/towards this bank.
For OUT transfer, a NAK handshake has been sent.
For Isochronous OUT transfer, an overrun condition has occurred.
For IN transfer, this bit is not valid. EPSTATUS.TRFAIL0 and EPSTATUS.TRFAIL1 should reflect the flow errors.
| Value | Description |
|---|---|
| 0 | No Error Flow detected. |
| 1 | A Error Flow has been detected. |
Bit 0 – CRCERR CRC Error
This bit defines the CRC Error Status.
This bit is set when a CRC error has been detected in an isochronous OUT endpoint bank.
| Value | Description |
|---|---|
| 0 | No CRC Error. |
| 1 | CRC Error detected. |