16.4 Boot ROM Dependencies

The Boot ROM is designed to operate based on user-configured boot settings defined in the BOOTCFG1/1A and ROMCFG fuses. No external hardware connections are required for Boot ROM operation.

Note: Users must ensure that the BOOT_GPIOSEL fuse is configured in a way that does not interfere with the overall hardware functionality of the application.

Clocks

The Boot ROM executes using the device’s default clock source: a 48 MHz DFLL (Digital Frequency Locked Loop) operating in open-loop mode. This clock is automatically enabled by the hardware following any type of reset, such as Power-on Reset, External Reset, and Watchdog Reset.

This 48 MHz DFLL is the fixed and non-configurable clock source for Boot ROM execution. It ensures consistent and deterministic behavior during the early boot phase, prior to any user-configurable clock initialization.

The Boot ROM does not support switching to alternative clock sources. Any clock configuration changes must be performed by the user application after control is transferred from the Boot ROM.

Device Fuse Programming (BOOTCFG 1, BOOTCFG1A, and ROMCFG)

The Boot ROM reads the BOOTCFG1/1A and ROMCFG fuses and applies the selected user configuration to the device.

Warning: Incorrect fuse settings may prevent the device from booting successfully. In extreme cases, invalid fuse configurations may render the device permanently non-functional.

Debug Operations

For security reasons, debug access is disabled during Boot ROM execution, except when the device enters Park Mode. The Boot ROM supports both cold-plugging and hot-plugging, allowing a debugger to attempt entry into Boot Interactive Mode under specific conditions. Refer to the DSU chapter for additional information on cold and hot plugging mechanisms.