37.2 Rx Buffer and FIFO Element 1

Table 37-86. Register Bit Attribute Legend
SymbolDescriptionSymbolDescriptionSymbolDescription
RReadable bitHCCleared by Hardware(Grey cell)Unimplemented
WWritable bitHSSet by HardwareXBit is unknown at Reset
KWrite to clearSSoftware settable bit
Name: R1
Offset: 0x004
Reset: 0x00000000
Property: RW

Bit 3130292827262524 
 ANMFFIDX[6:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 2322212019181716 
   FDFBRSDLC[3:0] 
Access R/WR/WR/WR/WR/WR/W 
Reset 000000 
Bit 15141312111098 
 RXTS[15:8] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 
Bit 76543210 
 RXTS[7:0] 
Access R/WR/WR/WR/WR/WR/WR/WR/W 
Reset 00000000 

Bit 31 – ANMF Accepted Non-matching Frame

Acceptance of non-matching frames may be enabled via GFC.ANFS and GFC.ANFE

ValueDescription
0

Received frame matching filter index FIDX.

1

Received frame did not match any Rx filter element.

Bits 30:24 – FIDX[6:0] Filter Index

0-127 : Index of matching Rx acceptance filter element (invalid if ANMF = ‘1’)

Note: Range is 0 to SIDFC.LSS-1 for standard and 0 to XIDFC.LSE-1 for extended.

Bit 21 – FDF FD Format

ValueDescription
0

Standard frame format.

1

CAN FD frame format (new DLC-coding and CRC).

Bit 20 – BRS Bit Rate Search

ValueDescription
0

Frame received without bit rate switching.

1

Frame received with bit rate switching.

Bits 19:16 – DLC[3:0] Data Length Code

ValueDescription
0-8

CAN + CAN FD: received frame has 0-8 data bytes

9-15

CAN: received frame has 8 data bytes.

9-15

CAN FD: received frame has 12/16/20/24/32/48/64 data bytes

Bits 15:0 – RXTS[15:0] Rx Timestamp

Timestamp Counter value captured on start of frame reception. Resolution depending on configuration of the Timestamp Counter Prescaler TSCC.TCP