29.2 Features

The SUPC controls the following analog supply elements:

  • Voltage Regulator System
    • Capless voltage regulators called VREGSW is used in Active, Idle, and Standby modes to supply PD_CORE_SW power domain.
    • Capless voltage regulator called VREGRAM used in Active, Idle, Standby, and Hibernate modes to supply VDDCORE_RAM domain and PLL.
    • Low-Power voltage regulator in Backup mode (LPVREGC)
    • User LDO regulator to power an external component.
  • Voltage Reference System (Bandgap)
    • Reference voltage for ADC
    • Temperature sensor
    • Low-power mode in Standby Sleep mode
    • Charge Pump for I/O pad and analog cells, such as PTC/AC/ADC in case of low VDD voltage
  • 3.3V Brown-out Reset (BOR) Detector
    • Two instances of BOR are used when calibrated; one to monitor VDDIO and one to monitor VDDREG power supply voltages, during Power-up, Active and Standby Sleep modes
    • Programmable threshold value loaded from USER CFG page at startup
    • Triggers resets
    • Operating modes: Continuous mode and Low-power mode in Standby and Hibernate modes
  • 3.3V Low-Power Brown-out Reset (DCBOR)
    • Used in Backup mode to monitor VDDIO, AVDD and VDDREG
    • Threshold values loaded from USER CFG page of CFM Flash Memory
    • Triggers resets
    • Operating modes: Continuous mode and Sampled mode (with programmable sampling frequency)
  • 1.2V Brown-out Reset (BOR12)
    • Monitors VDDCORE power supply voltage
    • Tightly coupled with the capless regulator
    • Triggers resets
  • 3.3V Programmable Low-Voltage Detector
    • Monitors VDDIO
    • Configurable threshold and direction
    • Can trigger Interrupt and generate EVSYS Events
  • Output pins
    • Pin toggling on RTC event or by SUPC in Backup mode