47.2 Operation

A single clock is used for the APB interface and all internal logic. The CTRLA.ENABLE bit controls the operation of the clock. When CTRLA.ENABLE = 1, the clock is enabled in Active mode and Idle mode, otherwise it is disabled. Software must enable the macro by setting CTRLA.ENABLE = 1 before performing any operations to the internal control registers.

PUF has a single interrupt request. The Intrinsic PUF IP registers control enabling and reading status of Interrupt.

PUF has two DMA requests: data in and data out. For additional information on the DMA functionality, refer to the DMA chapter of the data sheet.

The CTRLA.PRIV bit controls access to PUF registers. When CTRLA.PRIV = 1, only privileged accesses are permitted to PUF registers, unprivileged accesses generate a bus error. When CTRLA.PRIV = 0 both privileged and unprivileged accesses are permitted.

The CTRLA and WPCTRL registers can be write locked. This is controlled through the WPCTRL.WPEN and WPCTRL.WPLCK bits.