5.2 FPGA Fabric Interface Clocks

PolarFire SoC and RT PolarFire SoC FPGAs provide multiple Fabric Interface Controllers (FIC) to enable connectivity between user logic in the FPGA fabric and the MSS. FIC is part of the MSS and acts as a bridge between MSS and the fabric. There are three 64-bit AXI4 FICs, one 32-bit APB interface FIC, and one 32-bit AHB-Lite interface FIC, see the following table.

Table 5-3. FICs in PolarFire SoC and RT PolarFire SoC FPGA
FIC InterfaceDescription
FIC0 and FIC1Each FIC provides two 64-bit AXI4 bus interfaces between the MSS and the Fabric. One of them is mastered by the MSS and has slaves in the fabric, the other is mastered by the fabric and has slaves in the MSS. Only FIC1 can be used for data transfers to or from the PCIe Controller hard block in the FPGA.
FIC2Provides a single 64-bit AXI4 bus interface between the MSS and the fabric. It is mastered by the fabric and has slaves in the MSS. It is only used to access non-cached DDR memory through the DDR controller inside the MSS block.
FIC3Provides a single 32-bit APB bus interface between the MSS and the fabric. It is mastered by the MSS and has slaves in the fabric. It can be used to configure PCIe and XCVR hard blocks.
FIC4This FIC is dedicated to interface with the User Crypto Processor. This provides two 32-bit AHB-Lite bus interfaces between the Crypto Processor and the fabric. One of them is mastered by the fabric and the crypto processor acts as a slave. The other is mastered by the DMA controller of the User Crypto Processor and has a slave in the fabric.

Each FIC can operate on a different clock frequency, defined as a ratio of the MSS main clock. The FIC is a hard block, which also contains a DLL, enabling or disabling it does not consume any user logic. If the frequency of the FIC block is greater than or equal to 125 MHz, then the DLL must be enabled for removing clock insertion delay. If the frequency of the FIC block is less than 125 MHz, then the DLL must be bypassed.

The Fabric side AXI interface of the FIC blocks; FIC0, FIC1, FIC2, and FIC3 can operate up to 250 MHz and the MSS side AXI interface of the FIC blocks can operate up to 312.5 MHz. The FIC4 can operate up to 200 MHz. The MSS and Fabric clocks are asynchronous in nature and the FIC block takes care of clock domain crossing.