4.2.3 Pseudo Instructions

The assembler synthesizes PIC32M pseudo instructions as shown in the following table.


`li rt, imm`	32-bit load immediate
`move rt, rs`	copies rs into `rt`
`la rt, addr`	a load from memory location
`jrs`	jump register jr `rs`
`abs rt, rs`	absolute value, `rt` = \|`rs`\|
`beq{l} rs, label`	branch equal to zero if `rs` == 0
`bge{ul} rs, rt, label`	branch greater than equal if `rs` >= `rt`
`bgt{ul} rs, rt, label`	branch greater than if `rs` > `rt`
`ble{ul} rs, rt, label`	branch less than equal if `rs` <= `rt`
`blt{ul} rs, rt, label`	branch less than if `rs` < `rt`
`bne{ul} rs, rt, label`	branch not equal to if `rs` != `rt`
`neg{u} rt`	negate rs place in rs `rs` = -`rs`
`rotr/ror rt, rs, n`	rotate right, rotate `rs` `n` bits right, result in `rt` #only pseudo insn before mips32r2
`rotl/rol rt, rs, n`	rotate left, rotate `rs` `n` bits left, result in `rt` #only pseudo insn before mips32r2
`sge{u} rd, rs, rt`	set greater than equal sets `rd` = 1 if `rs` >= `rt`
`sgt{u} rd, rs, rt`	set greater than sets `rd` = 1 if `rs` > `rt`
`sle{u} rd, rs, rt`	set less than equal sets `rd` = 1 if `rs` <= `rt`
`sne{u} rd, rs, rt`	set not equal sets `rd` = 1 if `rs` != `rt`

In the above, the bracketed letter u indicates unsigned operation and the letter l inidcates that the likely delay slot is only executed if the branch is taken.

Additionally, a two-operand form of all math and logic instructions is permitted, where the first register represents both rd and rt in the full 3-operand form of the instruction. For example add $t0, $t1 is encoded as add $t0, $t0, $t1.

Pseudo instructions for PIC32C/SAM devices are listed below.


`adr{cond}{.W} Rd, label`	Register version - Load address into `Rd`
`adr{cond} Rd, label`	PC relative version - Load Address into `Rd`
`adrl{cond} Rd, label`	Long version - Generate two instructions to load larger addresses into `Rd`
`cpy{cond} Rd, Rm`	Alias for `mov` instruction
`ldr{cond}{.W} Rt, =expr`	Loads Rt with 32-bit immediate or an address
`ldr{cond}{.W} Rt, =label_expr`	If `mov` or `mvn` cannot be used will use literal pool to place value and load from there
`mov32{cond} Rd, expr`	Load any 32-bit immediate or 32-bit address into `Rd`
`neg{cond} Rd, Rm`	`Rd`= -`Rm`, alias for `RSBS{cond} Rd, Rm, #0`
`und{cond}{.W} {#expr}`	Generate an undefined instruction for target arch - useful for forcing hard faults `expr` is used to set condition codes

In the above, the {cond} field is comprised of instruction suffices that control conditional execution and condition flag updates. This can be any of the following.


`S`	Set the condition flags after execution
`S{flag}`	Conditionally execute the instruction based on the `flag` condition code suffix, update the condition flags after execution
`{flag}`	Conditionally execute the instruction based on the `flag` condition code suffix , do not update the condition flags after execution
`{.W}`	Specify width of the generated instruction to be 16 or 32 bit

Assembly directives, such as .set noat, .set nomacro, and .set noreorder, disable these normally helpful features for cases where you require full control over the generated code. See Symbols that Control Code Generation.