4.1 PWM Timing Data

Table 4-1 provides PWM timing data assignments for all PGs. PG2 and PG6 utilize their own phase and duty cycle data registers, as they are on the secondary side and have different timings than the other six PGs on the primary side. As described earlier, the PGxTRIGA and PGxTRIGB registers are used for PWMxL timing, where the trigger B register holds the latest calculated period (MPER/AMPER) and trigger A has period/2 plus dead time low.

Table 4-1. PWM Timing Data
PG Instance	Period	Dead Time High	Duty Cycle High	Dead Time Low	Duty Cycle Low	Phase Offset	Assignment
PG1	PG1PER	MPHASE	MDC	PG1TRIGA – MDC	PG1TRIGB – PG1TRIGA	-------------	Bank 1, Primary
PG3	MPER	MPHASE	MDC	PG3TRIGA – MDC	PG3TRIGB – PG3TRIGA	PG1TRIGC	Bank 1, Primary
PG4	MPER	MPHASE	MDC	PG4TRIGA – MDC	PG4TRIGB – PG4TRIGA	PG1TRIGD	Bank 1, Primary

PG2	MPER	PG2PHASE	PG2DC	PG2TRIGA – MDC	PG2TRIGB – PG2TRIGA	-------------	Bank 1, Secondary
APG1	AMPER	AMPHASE	AMDC	APG1TRIGA – AMDC	APG1TRIGB – APG1TRIGA	PG1TRIGC	Bank 1, Secondary
APG2	AMPER	AMPHASE	AMDC	APG2TRIGA – AMDC	APG2TRIGB – APG2TRIGA	PG1TRIGD	Bank 1, Secondary

PG5	MPER	MPHASE	MDC	PG5TRIGA – MDC	PG5TRIGB – PG5TRIGA	PG2TRIGC	Bank 2, Primary
PG7	MPER	MPHASE	MDC	PG7TRIGA – MDC	PG7TRIGB – PG7TRIGA	PG5TRIGC	Bank 2, Primary
PG8	MPER	MPHASE	MDC	PG8TRIGA – MDC	PG8TRIGB – PG8TRIGA	PG5TRIGD	Bank 2, Primary

PG6	MPER	PG6PHASE	PG6DC	PG6TRIGA – MDC	PG6TRIGB – PG6TRIGA	PG2TRIGC	Bank 2, Secondary
APG3	AMPER	AMPHASE	AMDC	APG3TRIGA – AMDC	APG3TRIGB – APG3TRIGA	PG5TRIGC	Bank 2, Secondary
APG4	AMPER	AMPHASE	AMDC	APG4TRIGA – AMDC	APG4TRIGB – APG4TRIGA	PG5TRIGD	Bank 2, Secondary

Many of the registers are updated in real-time as the LLC control system directly modulates the switching frequency. The phase offset between the PGs is also updated with changes to the period.