3.1 MCC Generated Code

To generate this project using MPLAB® Code Configurator (MCC), follow the next steps:

  1. Create a new MPLAB X IDE project for PIC18F47Q10.
  2. Open MCC from the toolbar. More information on how to install the MCC plug-in can be found here.
  3. Go to Project Resources → System → System Module and do the following configuration:
    • Oscillator Select: HFINTOSC
    • HF Internal Clock: 64 MHz
    • Clock Divider: 1
    • In the Watchdog Timer Enable field in the WWDT tab, WDT Disabled has to be selected.
    • In the Programming tab, Low-Voltage Programming Enable has to be checked.
  4. From the Device Resources window, add TMR2, TMR4, TMR6, CCP1, CLC1, CLC2 and CLC3. Do the following configurations for each peripheral:
    1. Timer2 Configuration:
      • Enable Timer: checked
      • Timer Clock tab
        • Clock Source: FOSC/4
        • Prescaler: 1:1
        • Postscaler: 1:1
      • Timer Period: 1 us
      • Enable Timer Interrupt: unchecked
    2. Timer4 Configuration:
      • Enable Timer: checked
      • Timer Clock tab
        • Clock Source: FOSC/4
        • Prescaler: 1:1
        • Postscaler: 1:1
      • Timer Period: 2 us
      • Enable Timer Interrupt: unchecked
    3. Timer6 Configuration:
      • Enable Timer: checked
      • Timer Clock tab
        • Clock Source: FOSC/4
        • Prescaler: 1:1
        • Postscaler: 1:1
      • Timer Period: 16 us
      • Enable Timer Interrupt: unchecked
    4. CCP1 Configuration:
      • Enable CCP: checked
      • CCP Mode: PWM
      • Select Timer: Timer6
      • Duty Cycle: 50%
      • CCPR Alignment: right_aligned
    5. CLC1 Configuration:
      • Enable CLC: checked
      • Mode: J-K flip-flop with R
      • The J-K flip-flop with R user configurable interpretation window is now available in the CLC1 window. Set the internal connections as shown below. By selecting TMR2 as clock source for the J-K, the CLC will generate a PWM signal with 500 kHz frequency and 50% duty cycle. Select CCP1 as the J input, allowing to have O = 0 when J is 0 and K is 1.
      Figure 3-3. CLC1 Configuration Mode J-K Flip-Flop with R
    6. CLC2 Configuration:
      • Enable CLC: checked
      • Mode: J-K flip-flop with R
      • The J-K flip-flop with R user configurable interpretation window is now available in the CLC2 window. Set the internal connections as shown below. By selecting TMR as clock source for the J-K, the CLC will generate a PWM signal with 250 kHz frequency and 50% duty cycle. Select CCP1 as the J input, allowing to have O = 0 when J is 0 and K is 1.
      Figure 3-4. CLC2 Configuration Mode J-K Flip-Flop with R
    7. CLC3 Configuration:
      • Enable CLC: checked
      • Mode: AND-OR
      • The AND-OR user configurable interpretation window is now available in the CLC3 window. Set the internal connections as shown below. By selecting CLC1 as both inputs for the AND, it becomes the first input of the OR. The same is true for CLC2 as second input of OR; this way CLC3 is used as a 2-input OR gate.
      Figure 3-5. CLC3 Configuration Mode AND-OR, Used as 2-Input OR
  5. In the Pin Manager: Grid View window, select the I/O pins outputs to enable the internal signal access to the I/O as shown in Figure 3-6.
    Figure 3-6. Pin Mapping for the Example “Using CLCs to Create a Data Signal Modulator”
  6. In the Project Resources window, click Generate.

For this example, no extra code was used aside from the one generated from MCC.