2.1 MCC Generated Code

To generate this project using MPLAB® Code Configurator (MCC), follow the next steps:

  1. Create a new MPLAB X IDE project for PIC18F47Q10.
  2. Open MCC from the toolbar. More information on how to install the MCC plug-in can be found here.
  3. Go to Project Resources → System → System Module and do the following configuration:
    • Oscillator Select: HFINTOSC
    • HF Internal Clock: 64 MHz
    • Clock Divider: 1
    • In the Watchdog Timer Enable field in the WWDT tab, WDT Disabled has to be selected.
    • In the Programming tab, Low-Voltage Programming Enable has to be checked.
  4. From the Device Resources window, add TMR2, TMR4, PWM3, PWM4, CLC1, CLC2 and CLC3. Do the following configurations for each peripheral:
    1. Timer2 Configuration:
      • Enable Timer: checked
      • Timer Clock tab
        • Clock Source: FOSC/4
        • Prescaler: 1:1
        • Postscaler: 1:1
      • Timer Period: 10 us
      • Enable Timer Interrupt: unchecked
    2. Timer4 Configuration:
      • Enable Timer: checked
      • Ext Reset Source: TMR2_postscaled
      • Start/Reset Options: Resets at rising TMR4_rst
      • Timer Clock tab
        • Clock Source: FOSC/4
        • Prescaler: 1:1
        • Postscaler: 1:1
      • Timer Period: 5 us
      • Enable Timer Interrupt: unchecked
    3. PWM3 Configuration:
      • Enable PWM: checked
      • Select a Timer: Timer2
      • Duty Cycle: 50%
      • PWM Polarity: active_hi
    4. PWM4 Configuration:
      • Enable PWM: checked
      • Select a Timer: Timer4
      • Duty Cycle: 50%
      • PWM Polarity: active_hi
    5. CLC1 Configuration:
      • Enable CLC: checked
      • Mode: AND-OR
      • The AND-OR user configurable interpretation window is now available in the CLC1 window. Set the internal connections as shown below. By selecting PWM3 as both inputs for the AND, it becomes the first input of the OR. The same is true for PWM4 as second input of OR; this way CLC1 is used as a 2-input OR gate.
      Figure 2-5. CLC1 Configuration Mode AND-OR, Used as 2-Input OR
    6. CLC2 Configuration:
      • Enable CLC: checked
      • Mode: 4-input AND
      • The 4-input AND user configurable interpretation window is now available in the CLC2 window. Set the internal connections as shown below. By selecting PWM3 as two of the inputs for the 4-input AND, and PWM4 as the other two, it becomes equivalent to a 2-input AND function from CLC2.
      Figure 2-6. CLC2 Configuration Mode 4-Input AND, Used as 2-Input AND
    7. CLC3 Configuration:
      • Enable CLC: checked
      • Mode: 4-input OR-XOR
      • The OR-XOR user configurable interpretation window is now available in the CLC3 window. Set the internal connections as shown below. By selecting PWM3 as both inputs for the OR, it becomes the first input of the XO. The same is true for PWM4 as second input of XOR; this way CLC3 is used as a 2-input XOR gate.
      Figure 2-7. CLC3 Configuration Mode OR-XOR, Used as 2-Input XOR
  5. In the Pin Manager: Grid View window, select the I/O pins outputs to enable the internal signal access to the I/O as shown in Figure 2-8.
    Figure 2-8. Pin Mapping for the Example “Using Basic Logic Gates”
  6. In the Project Resources window, click Generate.

For this example, no extra code was used aside from the one generated from MCC.