11.1.5.3 BSR Mode Entry and Wake-Up

The following figure shows the recommended power-down sequence to place the device in BSR mode (Backup Mode with SDRAM in Self-refresh mode to save the context). A combination of the LPM and SHDN signals, both outputs of the Shutdown Controller (SHDWC), requests a special powering mode to the external power supply where VDDIODDR is maintained. These outputs are supplied by VBAT present in BSR mode. In a similar way to the power-down sequence, the NRST signal must be asserted prior to turning the SAMA7G5 power supplies off.

Figure 11-6. Recommended Power Sequence at BSR Mode Entry

Table 11-14. BSR Mode Entry Timing Specification
Symbol	Parameter	Conditions	Min	Max	Unit
t_SHDN	SHDN delay at backup mode entry	Delay from SHDN low to NRST low	0	–	ms
t_RSTPD	NRST delay at power-down	Delay from NRST low to the first supply out of its operating range	0	–	ms

The following figure shows the recommended power-up sequence to wake up the device from BSR mode. Upon a Wake-up event (WKUP pin, RTC alarm, etc.), the Shutdown Controller automatically toggles its SHDN output back to VBAT to request the external power supply to restart. This power-up sequence is the same as the one shown in Figure 11-2. In particular, the supply groups definition is the same. The LPM pin is not automatically reset, and therefore the external power supply may enter a power saving state at wake-up. To make the power supply return to normal operation, the LPM pin must be software-reset in the SHDWC as soon as possible in the wake-up process.

Figure 11-7. Recommended Power Sequence at Wake-Up from BSR Mode

Table 11-15. Wake-Up from BSR Mode Timing Specification⁽¹⁾
Symbol	Parameter	Conditions	Min	Max	Unit
t₀	VDDIN33 delay	Delay from SHDN high to VDDIN33 turn-on	0	–	ms
t₁	VDDIN33 to periphery group delay	Delay from established VDDIN33 to the first periphery group supply established	-0.3	–	ms
t₂	Periphery group to VDDCORE delay	Delay from the last periphery group established supply to VDDCORE supply turn-on	0	–	ms
t₃	Reset delay at power-up	From established VDDCORE to NRST high	8	–	ms

Note:

The term "established" refers to a power supply established at 90% of its final value.