5.1 MAC

The ATWINC15x0B MAC is designed to operate at low power while providing high data throughput. The IEEE 802.11 MAC functions are implemented with a combination of dedicated datapath engines, hardwired control logic and a low-power, high-efficiency microprocessor. The combination of dedicated logic with a programmable processor provides optimal power efficiency and real-time response while providing the flexibility to accommodate evolving standards and future feature enhancements.

Dedicated datapath engines are used to implement datapath functions with heavy computational requirements. For example, an FCS engine checks the CRC of the transmitting and receiving packets, and a cipher engine performs all the required encryption and decryption operations for the WEP, WPA-TKIP and WPA2 CCMP-AES.

The control functions which have real-time requirements are implemented using hardwired control logic modules. These logic modules offer real-time response while maintaining configurability via the processor. Examples of hardwired control logic modules are the channel access control module (implements EDCA/HCCA, beacon TX control, interframe spacing and so on), protocol timer module (responsible for the Network Access Vector, back-off timing, timing synchronization function and slot management), MPDU handling module, aggregation/de-aggregation module, block ACK controller (implements the protocol requirements for burst block communication) and TX/RX control FSMs (coordinate data movement between PHY-MAC interface, cipher engine and the DMA interface to the TX/RX FIFOs).

The MAC functions implemented solely in software on the microprocessor have the following characteristics:

  • Functions with high memory requirements or complex data structures. Examples are association table management and power save queuing.
  • Functions with low computational load or without critical real-time requirements. Examples are authentication and association.
  • Functions which need flexibility and upgradeability. Examples are beacon frame processing and QoS scheduling.