9 Reference Design

Figure 9-1. ATWINC15x0B Reference Schematic Design (1, 2)
Note:
  1. Add test points for I2C_SCL (32) and I2C_SDA (33) pins.
  2. Add test points for UART TxD (12) and RxD (19) pins.
  3. Add a 10 µF and 0.01 µF decoupling capacitor to 1P3V net. Refer to Power Management Unit for layout guidelines.