4.6.3.2 Design Layout Recommendations

When designing the NAND Flash interface, consider the following recommendations:

• Match signal lengths to within 50 mils. Affected PIOs in the example schematic above are PA0 to PA7. For EMI improvement, all these nets should be placed in inner layers.
• Place data signals at least 2 times the trace width away from any other data trace.
• Place data signals at least 1 trace width away from any copper plan.