1 Electrical Characteristics

Table 1-1. Absolute Maximum Ratings
Parameter	Symbol	Value
Storage Temperature	T_S	–55°C to +125°C
Soldering Temperature/Time	T_LS	260°C / 10 sec.
Supply Voltage	V_DD	–0.3V to +4.5V

Note: Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied at these or any other conditions in excess of the conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Permanent damage is also possible if E/D is applied before VDD.

Table 1-2. ESD Ratings
Model	Minimum	Conditions
Human Body Model	2000V	MIL-STD-883, Method 3015
Charged Device Model	750V	JESD22-C101

Note: Although ESD protection circuitry has been designed into the VC-870, proper precautions should be taken when handling and mounting. Microchip employs a human body model (HBM) and a charged device model (CDM) for ESD susceptibility testing and design protection evaluation.

Table 1-3. 3.3V Electrical Performance
Parameter	Symbol	Min.	Typ.	Max.	Units	Conditions
Supply
Voltage	V_DD	3.0	3.3	3.6	V	Note 1
Maximum Voltage	V_DD(MAX)	–0.3	—	4.5	V	—
Current	I_DD	—	—	2.4	mA	≤40.000MHz, Note 2
		—	—	4.2	mA	>40.000MHz, Note 2
		—	—	10	µA	Output Disabled
Frequency
Nominal Frequency	f_NOM	0.54875	—	80	MHz	—
Stability	f_STAB	—	—	±25	ppm	Ordering Option
		—	—	±50
		—	—	±100
Outputs
Output Logic Level High	V_OH	0.9 x V_DD	—	—	V	Note 2
Output Logic Level Low	V_OL	—	—	0.1 x V_DD	V	Note 2
Load	C_LOAD	—	—	15	pF	—
Output Rise/Fall Time	t_R/t_F	—	—	3	ns	Note 2
Duty Cycle	DC	45	50	55	%	Note 3
Period Jitter, RMS	Φ_J	—	2.2	—	ps	—
Period Jitter, Peak-to-Peak	Φ_J	—	20	—	ps	—
Enable/Disable
Output Enable	V_IH	0.7 x V_DD	—	—	V	Note 4
Output Disable	V_IL	—	—	0.3 x V_DD	V	Note 4
Disable Time	t_DIS	—	—	200	ns	—
Start-Up Time	t_SU	—	—	2	ms	—
Operating Temperature	T_OP	–20	—	+70	°C	Ordering Option
Operating Temperature	T_OP	–40	—	+85	°C	Ordering Option
Notes: The power supply should have bypass capacitors as close to the supply and to ground as possible (for example, 0.1µF and 0.01µF). Parameters are tested with the production test circuit in Figure 1-1. Duty Cycle is measured as On-Time/Period (see Figure 1-2). A 10kΩ pull-up resistor to VDD is recommended if the E/D pin is unused.

Table 1-4. 2.5V Electrical Performance
Parameter	Symbol	Min.	Typ.	Max.	Units	Conditions
Supply
Voltage	V_DD	2.25	2.5	2.75	V	Note 1
Maximum Voltage	V_DD(MAX)	–0.3	—	4.5	V	—
Current	I_DD	—	—	2.0	mA	≤40.000MHz, Note 2
		—	—	3.4	mA	>40.000MHz, Note 2
		—	—	10	µA	Output Disabled
Frequency
Nominal Frequency	f_NOM	0.54875	—	80	MHz	—
Stability	f_STAB	—	—	±25	ppm	Ordering Option
		—	—	±50
		—	—	±100
Outputs
Output Logic Level High	V_OH	0.9 x V_DD	—	—	V	Note 2
Output Logic Level Low	V_OL	—	—	0.1 x V_DD	V	Note 2
Load	C_LOAD	—	—	15	pF	—
Output Rise/Fall Time	t_R/t_F	—	—	5	ns	Note 2
Duty Cycle	DC	45	50	55	%	Note 3
Period Jitter, RMS	Φ_J	—	2.2	—	ps	—
Period Jitter, Peak-to-Peak	Φ_J	—	20	—	ps	—
Enable/Disable
Output Enable	V_IH	0.7 x V_DD	—	—	V	Note 4
Output Disable	V_IL	—	—	0.3 x V_DD	V	Note 4
Disable Time	t_DIS	—	—	150	ns	—
Start-Up Time	t_SU	—	—	2	ms	—
Operating Temperature	T_OP	–20	—	+70	°C	Ordering Option
Operating Temperature	T_OP	–40	—	+85	°C	Ordering Option
Notes: The power supply should have bypass capacitors as close to the supply and to ground as possible (for example, 0.1µF and 0.01µF). Parameters are tested with the production test circuit in Figure 1-1. Duty Cycle is measured as On-Time/Period (see Figure 1-2). A 10kΩ pull-up resistor to VDD is recommended if the E/D pin is unused.

Table 1-5. 1.8V Electrical Performance
Parameter	Symbol	Min.	Typ.	Max.	Units	Conditions
Supply
Voltage	V_DD	1.6	1.8	2.0	V	Note 1
Maximum Voltage	V_DD(MAX)	–0.3	—	4.5	V	—
Current	I_DD	—	—	4.0	mA	≤40.000MHz, Note 2
		—	—	6.0	mA	>40.000MHz, Note 2
		—	—	10	µA	Output Disabled
Frequency
Nominal Frequency	f_NOM	0.54785	—	80	MHz	—
Stability	f_STAB	—	—	±25	ppm	Ordering Option
		—	—	±50
		—	—	±100
Outputs
Output Logic Level High	V_OH	0.9 x V_DD	—	—	V	Note 2
Output Logic Level Low	V_OL	—	—	0.1 x V_DD	V	Note 2
Load	C_LOAD	—	—	15	pF	—
Output Rise/Fall Time	t_R/t_F	—	—	5	ns	Note 2
Duty Cycle	DC	45	50	55	%	Note 3
Period Jitter, RMS	Φ_J	—	2.2	—	ps	—
Period Jitter, Peak-to-Peak	Φ_J	—	20	—	ps	—
Enable/Disable
Output Enable	V_IH	0.7 x V_DD	—	—	V	Note 4
Output Disable	V_IL	—	—	0.3 x V_DD	V	Note 4
Disable Time	t_DIS	—	—	200	ns	—
Start-Up Time	t_SU	—	—	2	ms	—
Operating Temperature	T_OP	–20	—	+70	°C	Ordering Option
Operating Temperature	T_OP	–40	—	+85	°C	Ordering Option
Notes: The power supply should have bypass capacitors as close to the supply and to ground as possible (for example, 0.1µF and 0.01µF). Parameters are tested with the production test circuit in Figure 1-1. Duty Cycle is measured as On-Time/Period (see Figure 1-2). A 10kΩ pull-up resistor to VDD is recommended if the E/D pin is unused.