5.4.7 Interrupt Mask 1 Register


Bit	15	14	13	12	11	10	9	8
				SQIM	PSTCM	TXCOLM	TXJABM	TSSIM
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1


Bit	7	6	5	4	3	2	1	0
	EMPCYCM	RXINTOM	UNEXPBM	BCNBFTOM	UNCRSM	PLCASYMM	ESDERRM	DEC5BM
Access	R/W	R/W	R/W	R/W	R/W	R/W	R/W	R/W
Reset	1	1	1	1	1	1	1	1

Bit 12 – SQIM Signal Quality Indication Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the Signal Quality Indication (SQI) status bit is set.

Value	Description
`0`	SQI status interrupt enabled.
`1`	SQI status interrupt disabled.

Bit 11 – PSTCM PLCA Status Changed Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the PLCA Status Changed (PSTC) status bit is set.

Value	Description
`0`	PLCA status change interrupt enabled.
`1`	PLCA status change interrupt disabled.

Bit 10 – TXCOLM Transmit Collision Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the Transmit Collision (TXCOL) status bit is set.

Value	Description
`0`	Transmit collision interrupt enabled
`1`	Transmit collision interrupt disabled

Bit 9 – TXJABM Transmit Jabber Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the Transmit Jabber (TXJAB) status bit is set.

Value	Description
`0`	Transmit jabber interrupt enabled
`1`	Transmit jabber interrupt disabled

Bit 8 – TSSIM Time Synchronization Service Interface Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the Time Synchronization Service Interface (TSSI) status bit is set.

Value	Description
`0`	TSSI interrupt enabled
`1`	TSSI interrupt disabled

Bit 7 – EMPCYCM PLCA Empty Cycle Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the PLCA Empty Cycle (EMPCYC) status bit is set.

Value	Description
`0`	PLCA empty cycle interrupt enabled
`1`	PLCA empty cycle interrupt disabled

Bit 6 – RXINTOM Receive in Transmit Opportunity Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the Receive in Transmit Opportunity (RXINTO) status bit is set.

Value	Description
`0`	Receive in transmit opportunity interrupt enabled
`1`	Receive in transmit opportunity interrupt disabled

Bit 5 – UNEXPBM Unexpected BEACON Received Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the Unexpected BEACON Received (UNEXPB) status bit is set.

Value	Description
`0`	Unexpected BEACON received interrupt enabled
`1`	Unexpected BEACON received interrupt disabled

Bit 4 – BCNBFTOM BEACON Received Before Transmit Opportunity Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the BEACON Received Before Transmit Opportunity (BCNBFTO) status bit is set.

Value	Description
`0`	BEACON received before transmit opportunity interrupt enabled
`1`	BEACON received before transmit opportunity interrupt disabled

Bit 3 – UNCRSM Unexpected Carrier Sense Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the Unexpected Carrier Sense (UNCRS) status bit is set.

Value	Description
`0`	Unexpected carrier sense interrupt enabled
`1`	Unexpected carrier sense interrupt disabled

Bit 2 – PLCASYMM PLCA Symbols Detected Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the PLCA Symbols Detected (PLCASYM) status bit is set.

Value	Description
`0`	PLCA BEACON symbols detected interrupt enabled
`1`	PLCA BEACON symbols detected interrupt disabled

Bit 1 – ESDERRM End-of-Stream Delimiter Error Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the End-of-Stream Delimiter Error (ESDERR) status bit is set.

Value	Description
`0`	ESD error interrupt enabled
`1`	ESD error interrupt disabled

Bit 0 – DEC5BM 5B Decode Error Interrupt Mask

When clear, this bit will enable assertion of the IRQ_N pin when the 5B Decoder Error (DEC5B) status is set.

Value	Description
`0`	5B decode error interrupt enabled
`1`	5B decode error interrupt disabled

Name:	IMSK1
Address:	0x001C

LAN8670/1/2