5.2.5 10BASE-T1S Test Mode Control
| Name: | T1STSTCTL |
| Address: | 0x08FB |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| TSTCTL[2:0] | |||||||||
| Access | R/W | R/W | R/W | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| Access | RO | RO | RO | RO | RO | RO | RO | RO | |
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
Bits 15:13 – TSTCTL[2:0] Test Mode Control
This field configures and enables the various IEEE specified test modes. For a description of the test modes, refer to Clause 147.5.2 of the IEEE Std 802.3‑2022.
| Value | Description |
|---|---|
000 | Normal (non-test) operation |
001 | Test mode 1 - Transmitter output voltage, timing jitter |
010 | Test mode 2 - Transmitter output droop |
011 | Test mode 3 - Transmitter PSD mask |
100 | Test mode 4 - Transmitter high impedance mode |
101 | Reserved |
11x | Reserved |