34.5 Register Summary - Analog Peripheral Manager


Offset	Name	Bit Pos.	7	6	5	4	3	2	1	0
0x00 ... 0x1F4B	Reserved
0x1F4C	APMCON	7:0	EN
0x1F4D	APMPRE	7:0	PRE[7:0]
0x1F4D	APMPRE	15:8	PRE[15:8]
0x1F4F	APMPER	7:0	PER[7:0]
0x1F4F	APMPER	15:8	PER[15:8]
0x1F51	APMSTART1	7:0	START1[7:0]
0x1F51	APMSTART1	15:8	START1[15:8]
0x1F53	APMPERS1	7:0	TEMP	ADCA	ADCD	FVR2	FVR1	BG	POSC	SOSC
		15:8	ZCD	CMPLP1	CMP1		DAC2	DAC1	OPA2	OPA1
		23:16	VREFLP	VREFLPDAC					OPA4	OPA3
0x1F56	APMSTART2	7:0	START2[7:0]
		15:8	START2[15:8]
		23:16	START2[23:16]
0x1F59	APMPERS2	7:0	TEMP	ADCA	ADCD	FVR2	FVR1	BG	POSC	SOSC
		15:8	ZCD	CMPLP1	CMP1		DAC2	DAC1	OPA2	OPA1
		23:16	VREFLP	VREFLPDAC					OPA4	OPA3
0x1F5C	APMEND1	7:0	END1[7:0]
		15:8	END1[15:8]
		23:16	END1[23:16]
0x1F5F	APMPERE1	7:0	TEMP	ADCA	ADCD	FVR2	FVR1	BG	POSC	SOSC
		15:8	ZCD	CMPLP1	CMP1		DAC2	DAC1	OPA2	OPA1
		23:16	VREFLP	VREFLPDAC					OPA4	OPA3
0x1F62	APMEND2	7:0	END2[7:0]
		15:8	END2[15:8]
		23:16	END2[23:16]
0x1F65	APMPERE2	7:0	TEMP	ADCA	ADCD	FVR2	FVR1	BG	POSC	SOSC
		15:8	ZCD	CMPLP1	CMP1		DAC2	DAC1	OPA2	OPA1
		23:16	VREFLP	VREFLPDAC					OPA4	OPA3
0x1F68	APMCLK	7:0							CLK[1:0]
0x1F69	APMSTATUS	7:0	TEMP	ADCA	ADCD	FVR2	FVR1	BG	POSC	SOSC
		15:8	ZCD	CMPLP1	CMP1		DAC2	DAC1	OPA2	OPA1
		23:16	VREFLP	VREFLPDAC					OPA4	OPA3