39.11.1 CMLPxCON0
| Name: | CMLPxCON0 |
| Offset: | 0x0810 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| EN | OUT | POL | SYNC | ||||||
| Access | R/W | R | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 |
Bit 7 – EN Low-Power Comparator Enable
| Value | Description |
|---|---|
| 1 | LP Comparator is enabled |
| 0 | LP Comparator is disabled and consumes no active power |
Bit 6 – OUT Low-Power Comparator Output
| Value | Name | Description |
|---|---|---|
| 1 | If POL = 0 (noninverted
polarity): |
CLPxVP > CLPxVN |
| 0 | If POL = 0 (noninverted
polarity): |
CLPxVP < CLPxVN |
| 1 | If POL = 1 (inverted
polarity): |
CLPxVP < CLPxVN |
| 0 | If POL = 1 (inverted
polarity): |
CLPxVP > CLPxVN |
Bit 4 – POL Low-Power Comparator Output Polarity Select
| Value | Description |
|---|---|
1 |
LP Comparator output is inverted |
0 |
LP Comparator output is not inverted |
Bit 0 – SYNC Low-Power Comparator Output Synchronous Mode
| Value | Description |
|---|---|
| 1 | LP Comparator output to Timer1 and I/O pin is synchronous to changes on Timer1 clock source. Output updated on the falling edge of Timer1 clock source. |
| 0 | LP Comparator output to Timer1 and I/O pin is asynchronous |
