17.3.5 PORTWIN2
Note:
- This register can only be written when the clock to the module is disabled. See Signal Routing Port Clock section for details.
| Name: | PORTWIN2 |
| Offset: | 0x1F26 |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| IN[3:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | |||||
| Reset | 0 | 0 | 0 | 0 | |||||
Bits 3:0 – IN[3:0] Signal Routing Port Input Selection
| Reset States: |
|
