17.3.13 PORTWCON
| Name: | PORTWCON |
| Offset: | 0x1F2E |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| CPOL | CLKEN | ||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 |
Bit 4 – CPOL PORTW Clock Polarity
| Value | Description |
|---|---|
| 1 | Falling-edge clock. |
| 0 | Rising-edge clock. |
Bit 0 – CLKEN PORTW Clock Enable
| Reset States: |
|
| Value | Description |
|---|---|
| 1 | Clock input for PORTW is enabled. All PORTW registers are read-only, except LATW which is read/write. |
| 0 | Clock input for PORTW is disabled. All PORTW registers, including LATW, have read/write access. |