36.14 TWI

Figure 36-7. TWI - Timing Requirements
Table 36-20. TWI - Timing Characteristics
SymbolDescriptionConditionMin.Typ.Max.Unit
fSCLSCL clock frequencyMax. frequency requires the system clock running at 10 MHz, which, in turn, requires VDD = [2.7, 5.5]V and T = [-40, 105]°C0-1000kHz
VIHInput high voltage0.7 × VDD--V
VILInput low voltage--0.3 × VDDV
VHYSHysteresis of Schmitt trigger inputs0.1 × VDD0.4 × VDDV
VOLOutput low voltageIload = 20 mA, Fast mode+--0.2 × VDDV
Iload = 3 mA, Normal mode, VDD > 2V--0.4
Iload = 3 mA, Normal mode, VDD ≤ 2V--0.2 × VDD
IOLLow-level output currentfSCL ≤ 400 kHz, VOL = 0.4V3--mA
fSCL ≤ 1 MHz, VOL = 0.4V20--
CBCapacitive load for each bus linefSCL ≤ 100 kHz--400pF
fSCL ≤ 400 kHz--400
fSCL ≤ 1 MHz--550
tRRise time for both SDA and SCLfSCL ≤ 100 kHz--1000ns
fSCL ≤ 400 kHz20-300
fSCL ≤ 1 MHz--120
tOFOutput fall time from VIHmin to VILmax10 pF < Capacitance of bus line < 400 pFfSCL ≤ 400 kHz20 × (VDD/5.5V)-250ns
fSCL ≤ 1 MHz20 × (VDD/5.5V)-120
tSPSpikes suppressed by Input filter0-50ns
ILInput current for each I/O pin0.1×VDD < VI < 0.9×VDD--1µA
CICapacitance for each I/O pin--10pF
RPValue of pull-up resistorfSCL ≤ 100 kHz(VDD - VOL(max)) /IOL-1000 ns/(0.8473 × CB)Ω
fSCL ≤ 400 kHz--300 ns/(0.8473 × CB)
fSCL ≤ 1 MHz--120 ns/(0.8473 × CB)
tHD;STAHold time (repeated) Start conditionfSCL ≤ 100 kHz4.0--µs
fSCL ≤ 400 kHz0.6--
fSCL ≤ 1 MHz0.26--
tLOWLow period of SCL ClockfSCL ≤ 100 kHz4.7--µs
fSCL ≤ 400 kHz1.3--
fSCL ≤ 1 MHz0.5--
tHIGHHigh period of SCL ClockfSCL ≤ 100 kHz4.0--µs
fSCL ≤ 400 kHz0.6--
fSCL ≤ 1 MHz0.26--
tSU;STASetup time for a repeated Start conditionfSCL ≤ 100 kHz4.7--µs
fSCL ≤ 400 kHz0.6--
fSCL ≤ 1 MHz0.26--
tHD;DATData hold timefSCL ≤ 100 kHz0-3.45µs
fSCL ≤ 400 kHz0-0.9
fSCL ≤ 1 MHz0-0.45
tSU;DATData setup timefSCL ≤ 100 kHz250--ns
fSCL ≤ 400 kHz100--
fSCL ≤ 1 MHz50--
tSU;STOSetup time for Stop conditionfSCL ≤ 100 kHz4--µs
fSCL ≤ 400 kHz0.6--
fSCL ≤ 1 MHz0.26--
tBUFBus free time between a Stop and Start conditionfSCL ≤ 100 kHz4.7--µs
fSCL ≤ 400 kHz1.3--
fSCL ≤ 1 MHz0.5--
Table 36-21. SDA Hold Time(1,2)
SymbolDescriptionConditionMin.Typ.Max.Unit
tHD;DATData hold timeMaster(3)fCLK_PER = 5 MHzSDAHOLD = 0x00-800-ns
SDAHOLD = 0x01830850950
SDAHOLD = 0x02830850950
SDAHOLD = 0x038308501270
fCLK_PER = 10 MHzSDAHOLD = 0x00-400-
SDAHOLD = 0x01430450550
SDAHOLD = 0x02430450580
SDAHOLD = 0x034305501270
fCLK_PER = 20 MHzSDAHOLD = 0x00-200220
SDAHOLD = 0x01230250350
SDAHOLD = 0x02260450580
SDAHOLD = 0x033806001270
tHD;DATData hold timeSlave(4)All FrequenciesSDAHOLD = 0x0090150220ns
SDAHOLD = 0x01130200350
SDAHOLD = 0x02260400580
SDAHOLD = 0x033905501270
Note:
  1. These parameters are for design guidance only and are not covered by production test limits.
  2. SDAHOLD is the data hold time after the SCL signal is detected as low. The actual hold time is, therefore, higher than the configured hold time.
  3. For Master mode, the data hold time is whatever is largest of the following:
    • 4 × tCLK_PER + 50 ns (typical)
    • SDAHOLD configuration + SCL filter delay
  4. For Slave mode, the hold time is given by:
    • SDAHOLD configuration + SCL filter delay