16.8 Programming

Programming the Flash or RAM memories is only possible when the device is not protected by the Code Protect bit.

Important: If securing the device using SECCFG.DEBUG_LCK, row programming is not supported because SRAM memory is not accessible by the external debugger. Either Word programming or Quad Word programming is possible based on the CFGCON0.ECCCTL setting.
The programming procedure is as follows:
  1. At power-up, MCLR is driven low by a debugger. The on-chip regulator holds the system in a POR state until the input supply is above the POR threshold (See Power-on Reset (POR) electrical characteristics from Related Links). The system is going to be in this Static state until the internally regulated supplies have reached a safe Operating state.
  2. The power management starts, clocks are switched to the Slow clock (Core Clock, System Clock, Flash Clock and any Bus Clocks that do not have clock gate control). Internal Resets are maintained due to the external Reset.
  3. The debugger maintains a low-level on SWCLK. MCLR is released, resulting in a debugger Cold-Plugging procedure.
  4. The debugger generates a clock signal on the SWCLK pin, the Debug Access Port (DAP) receives a clock.
  5. The CPU remains in Reset due to the Cold-Plugging procedure; meanwhile, the rest of the system is released.
  6. The user must issue a Chip Erase command to ensure the Flash is fully erased before programming.
  7. Programming is available through the AHB-AP. See PIC32CX-BZ3 Programming Specification and Flash Controller from Related Links.
    Note: Programming of Boot Flash Memory (BFM) pages is allowed only when the bit 3 at address 0x410001FC is set to ‘1’.
  8. Completing the operation, the chip can be restarted either by asserting MCLR, toggling power or writing a ‘1’ to the Status A register CPU Reset Phase Extension bit (STATUSA.CRSTEXT). Ensure that the SWCLK pin is high when releasing MCLR to prevent extending the CPU Reset.