16.7 Chip Erase

Chip erase consists of removing all sensitive information stored in the chip and clearing the Code Protect bit. Therefore, this erases all volatile memories and the Flash memory.
Note: The OTP Boot flash memory page will not be erased.
When the device is protected using the FCPN0.CP or SECCFG.DEBUG_LCK bit, the debugger must first Reset the device to be detected. This ensures that internal registers are reset after removing the Protected state. The user can trigger the chip erase operation by writing a ‘1’ to the Chip Erase bit in the Control register (CTRL.CE). This command will be discarded if the DSU is protected by the Peripheral Access Controller (PAC). After issuing, the module clears volatile memories prior to erasing the Flash array. To ensure the completion of the chip erase operation, check the Done bit of the Status A register (STATUSA.DONE).

The chip erase operation depends on clocks and power management features that can be altered by the CPU. For that reason, the recommendation is to issue a Chip Erase command after a Cold-Plugging procedure to ensure that the device is in a known and safe state.

The following is the recommended sequence:
  1. Issue the Cold-Plugging procedure (See Cold-Plugging from Related Links), then the device performs the following:
    1. Detects the debugger probe
    2. Holds the CPU in Reset
  2. Issue the Chip Erase command by writing a ‘1’ to CTRL.CE. The device, then:
    1. Clears the system volatile memories
    2. Erases the whole Flash array (excluding OTP)
    3. Erases the Lock Row and Code Protect bit protection
  3. Check for completion by polling STATUSA.DONE (read as ‘1’ when completed).
  4. Reset the device to let the Flash Controller update the fuses.