21.1 Overview
For safety applications, the PIC32CX-BZ3 family can embed error correction codes (ECC) to detect and correct single bit errors or to enable dual error detection in SRAM. As discussed in the Memories chapter, when the RAMECC is enabled, the top half of the SRAM memory will be reserved to store error correction codes and will not be available for the application. See SRAM Memory Configuration from Related Links.
ECC calculation is software-selectable through the CFGCON0.FRECCDIS bit in the Boot Flash Configuration. For additional information, see System Configuration and Register Locking (CFG) from Related Links.