8.6 SRAM Memory Configuration

Retention

Depending on the application and power budget needs, part of the system memory can be retained in the Deep Sleep mode. The amount of the SRAM retained in this mode is software selectable, by writing the WCMSIZ register in the PMU module, up to 32 KB of SRAM.

By default, no retention is selected.

RAM Error Correction

For safety applications, the PIC32CX-BZ3 family embeds Error Correction Codes (ECC) to detect and correct single bit errors or to enable dual error detection for the system memory. The ECC is software selectable through the DEVCFG0.FRECCDIS bit in the boot Flash device configuration. By default, ECC is disabled.

ECC can be applied only for 32 KB of SRAM. When enabled, the top 32 KB of memory is reserved to store the ECC, and it is not be available for the application.

Therefore, when ECC is enabled, the usable system RAM is 64 KB (96-32 KB) for the 96 KB data RAM variant. ECC support for row A or row B can be selected using the CFGCON1.ECC_SEL_MEM bit. If CFGCON1.ECC_SEL_MEM is ‘0’, ECC supports the contents in Row A. If CFGCON1.ECC_SEL_MEM is ‘1’, ECC supports the contents in row B.

CoreSight ETB Connection

When enabled, the bottom 32 KB system memory space is reserved for CoreSight (Embedded Trace Buffer) ETB debug usage. Therefore, when CoreSight ETB is enabled, the usable system RAM is 64 KB (96-32 KB) for the 96 KB data RAM variant. The following figure illustrates an example where both ECC and CoreSight ETB are enabled.