17.3.3 System and Peripheral Bus Clock Generation (CLKGEN)

The CLKGEN module generates and controls the synchronous clocks on the system. This includes the CPU, bus clocks (APB, AHB), as well as the synchronous (to the CPU) user interfaces of the peripherals. It contains prescalers for the CPU and bus clocks.

There are two types of clocks generated by this module, called system clocks and peripheral clocks:
  • The system clock (SYS_CLK used by the CPU supports components such as memory subsystems and fast peripherals.
  • The peripheral bus clocks (PB1_CLK, PB2_CLK and PB3_CLK) are used to clock slow peripheral devices attached to the pb_bus.
The PBx_CLK outputs are based on the SYS_CLK frequency with a fixed divisor. The divisor is determined by the value of the PBxDIV registers.

The system and peripheral bus clocks are stopped when in Sleep mode. The clocks are restarted by disabling the sleep enable.