33.6.4 DMA, Interrupts and Events

Table 33-4. Module Request for SERCOM SPI
ConditionRequest
DMA Interrupt Event
Data Register Empty (DRE)Yes

(request cleared when data are written)

YesNA
Receive Complete (RXC)Yes

(request cleared when data are read)

Yes
Transmit Complete (TXC)NAYes
SPI Select Low (SSL)NAYes
Error (ERROR)NAYes
Table 33-5. Module Request for SERCOM SPI
ConditionRequest
DMA Interrupt Event

Standard (DRE) – Data Register Empty

FIFO (DRE) – at least TXTRHOLD locations in TX FIFO are empty

Yes

(request cleared when data are written)

YesNA

Standard (RXC) – Receive Complete

FIFO (RXC) – at least RXTRHOLD data available in RX FIFO, or a last word available and length frame reception completed.

Yes

(request cleared when data are read)

Yes

Standard (TXC) – Transmit Complete

FIFO (TXC) – Transmit Complete and TX FIFO is empty

NAYes
SPI Select Low (SSL)NAYes
Error (ERROR)NAYes