33.6.6 Synchronization

Due to asynchronicity between the main clock domain and the peripheral clock domains, some registers need to be synchronized when written or read. When executing an operation that requires synchronization, the corresponding Synchronization Busy bit in the Synchronization register (SYNCBUSY) is set immediately and cleared when synchronization is complete. If an operation that requires synchronization is executed while the corresponding SYNCBUSY bit is one, a peripheral bus error is generated.

The following bits need to be synchronized when written:

• Software Reset bit in the CTRLA register (CTRLA.SWRST)
• Enable bit in the CTRLA register (CTRLA.ENABLE)
• Receiver Enable bit in the CTRLB register (CTRLB.RXEN)

Required write synchronization is denoted by the Write-Synchronized property in the register description.