35.2 Features

  • Host SPI Interface:
    • Programmable clock phase and clock polarity
    • Programmable transfer delays between consecutive transfers, between clock and data, between deactivation and activation of chip select
  • SPI Mode:
    • To use serial peripherals, such as ADCs, DACs, LCD controllers, CAN controllers and sensors
    • 8-bit, 16-bit or 32-bit programmable data length
  • Serial Memory Mode:
    • To use serial Flash memories operating in single-bit SPI, Dual SPI and Quad SPI
    • Supports Execute in Place (XIP). The system can execute code directly from a Serial Flash memory
    • Flexible instruction register to be compatible with all serial Flash memories
    • 32-bit Address mode (default is 24-bit address) to support serial Flash memories larger than 128 Mbit
    • Continuous Read mode
    • Scrambling/Unscrambling On-the-Fly
    • Double data rate support (Read only)
  • Connection to DMA Channel Capabilities Optimizes Data Transfers
    • One channel for the receiver and one channel for the transmitter
  • Register Write Protection