11.2 Features

  • Physically Addressed and Physically Tagged
  • L1 Data and Instruction Cache Set to 4 KB
  • L1 Cache Line Size Set to 16 Bytes
  • L1 Cache Integrates 32-Bit Bus Host Interface
  • Unified 4-Way Set Associative Cache Architecture
  • Lock-Down Feature, Which Allows Cached to be Locked Per Way
  • Write Through Cache Operations, Read Allocate
  • Configurable as Data and Instruction Tightly Coupled Memory (TCM)
  • Round Robin Victim Selection Policy
  • Event Monitoring, with One Programmable 32-Bit Counter
  • Cache Interface Includes Cache Maintenance Operations Registers