11.7 RAM Properties

The following table shows the different access properties of the three RAM blocks, according to the different modes described in the previous chapters.

Table 11-2. Access to RAM
Access ConditionData RAMTag RAMMetadata RAM
CPU access when CMCC DISABLEDRead/Writeno Read/Write - hardfaultno Read/Write - hardfault
CPU access when CMCC ENABLED CACHE section configured: Read/Write(1)

TCM section configured: Read/Write

no Read/Write - hardfaultno Read/Write - hardfault
Debugger access when CMCC DISABLEDRead/WriteRead/WriteRead/Write
Debugger access when CMCC ENABLEDCACHE section configured: Read/Write(1)

TCM section configured: R/W

no Read/Writeno Read/Write
CPU Test access when CMCC DISABLEDRead/WriteRead/WriteRead/Write
CPU Test access when CMCC ENABLEDCACHE section configured: Read/Write(1)

TCM section configured: Read/Write

no Read/Writeno Read/Write
Note:
  1. A write operation in this zone can corrupt the coherency of the cache. There is a need for an invalidate operation.