15.9 Error Correcting Code (ECC) and Flash Programming

The PIC32CX-BZ3 devices incorporate Error Correcting Code (ECC) features that detect and correct errors resulting in extended Flash memory life. For more details on this feature, see Prefetch Cache from Related Links.

ECC is implemented in 128-bit Quad Flash Words or 32-bit single Word. As a result, when programming Flash memory on a device with ECC, the programming operation must be, at minimum, four instruction Words or in groups of four instruction Words. This is the reason that the Quad Word programming command exists and why row programming always programs multiples of four Words.

For a given software application, ECC can be enabled at all times, disabled at all times or dynamically enabled using the ECCCTL Configuration bits in the CFGCON0 register. When ECC is enabled at all times, the single Word NVMOP programming command does not function and the Quad Word is the smallest unit of memory that can be programmed. If disabling or enabling the ECC dynamically, both the single Word and Quad Word programming NVMOP commands are functional and the programming method used determines how ECC is handled.

If dynamic ECC and if the memory was programmed with the single Word command, ECC is turned-off for that Word, and, when it is read, no error correction is performed. If the memory was programmed with the Quad Word or row programming commands, ECC data is written and tested for errors (and corrected if needed) when read. The following table describes the different ECC scenarios.