29.6.2.3 Measurement
After the FREQM is enabled, writing a
‘1
’ to the START bit in the Control B register (CTRLB.START) starts the
measurement. The BUSY bit in Status register (STATUS.BUSY) is set when the measurement
starts, and cleared when the measurement is complete.
There is also an interrupt request for Measurement Done: When the
Measurement Done bit in Interrupt Enable Set register (INTENSET.DONE) is
‘1
’ and a measurement is finished, the Measurement Done bit in the
Interrupt Flag Status and Clear register (INTFLAG.DONE) will be set and an interrupt
request is generated.
The result of the measurement can be read from the Value register (VALUE.VALUE). The frequency of the measured clock GCLK_FREQM_MSR is then:
- In order to make sure the measurement result (VALUE.VALUE[23:0]) is valid, the overflow status (STATUS.OVF) must be checked.
- Due to asynchronous operations, the VALUE Error measurement can be up to two samples.
If an overflow condition occurred, indicated by the overflow bit
in the STATUS register (STATUS.OVF), either the number of reference clock cycles must be
reduced (CFGA.REFNUM) or a faster reference clock must be configured. Once the
configuration is adjusted, clear the overflow status by writing a ‘1
’ to
STATUS.OVF. Then, another measurement can be started by writing a ‘1
’ to
CTRLB.START.