6.5.5.2.2 Output Mapping in PIC32CX-BZ3 Family of Devices

The following tables provide output mapping in PIC32CX-BZ3 family of devices.

Table 6-7. PPS Output Groups
Group 1Group 2Group 3Group 4
OFFOFFOFFOFF
SERCOM0_PAD1SERCOM0_PAD0OFFSERCOM0_PAD2
SERCOM1_PAD1SERCOM0_PAD3SERCOM0_PAD0OFF
REFO1SERCOM0_PAD2SERCOM0_PAD3SERCOM0_PAD0
REFO2OFFSERCOM1_PAD2SERCOM1_PAD3
REFO3SERCOM1_PAD3OFFOFF
REFO4SERCOM1_PAD2SERCOM1_PAD3SERCOM1_PAD0
QSPI_SCKTCC0_WO1TCC0_WO2TCC0_WO3
OFFTCC0_WO5TCC0_WO0TCC0_WO1
OFFTCC0_WO3TCC0_WO4TCC0_WO5
OFFTCC1_WO1TCC1_WO2TCC1_WO3
OFFTCC1_WO5TCC1_WO0TCC1_WO1
OFFTCC1_WO3TCC1_WO4TCC1_WO5
OFFTCC2_WO1TCC2_WO0TCC2_WO1
OFFOFFOFFOFF
OFFTC0_WO1TC0_WO0TC0_WO0
OFFTC1_WO1TC1_WO0TC1_WO1
OFFTC2_WO1TC2_WO0TC2_WO1
OFFTC3_WO1TC3_WO0TC3_WO1
OFFTC4_WO1TC4_WO0TC4_WO1
OFFTC5_WO1TC5_WO0TC5_WO1
OFFTC6_WO1TC6_WO0TC6_WO1
OFFTC7_WO1TC7_WO0TC7_WO1
OFFQSPI_CSQSPI_CSQSPI_CS
OFFQSPI_DATA0QSPI_DATA1QSPI_DATA2
OFFQSPI_DATA3QSPI_DATA0QSPI_DATA1
OFFQSPI_DATA2QSPI_DATA3QSPI_DATA0
OFFCCL_OUT1CCL_OUT0CCL_OUT1
Table 6-8. Remappable Output Pin Configuration – Group 1
RPn Port PinRPnG1R SFR RPnG1R Bits RPnG1R Value to Peripheral Pin Selection
RPA3 RPA3G1R RPA3G1R[4:0]

00000 = OFF

00001 = SERCOM0_PAD1

00010 = SERCOM1_PAD1

00011 = REFO1

00100 = REFO2

00101 = REFO3

00110 = REFO4

00111 = QSPI_SCK

01000 = OFF

01001 = OFF

01000 = OFF

01001 = OFF

01010 = OFF

01011 = OFF

01100 = OFF

01101 = OFF

01110 = OFF

01111 = OFF

10000 = OFF

10001 = OFF

10010 = OFF

10011 = OFF

10100 = OFF

10101 = OFF

10110 = OFF

10111 = OFF

11000 = OFF

11001 = OFF

11010 = OFF

11011 = OFF

11100 = OFF

11101 = OFF

11110 = OFF

11111 = OFF

RPA5RPA5G1RRPA5G1R[4:0]
RPA6RPA6G1RRPA6G1R[4:0]
RPA7RPA7G1RRPA7G1R[4:0]
RPB5RPB5G1RRPB5G1R[4:0]
RPB6RPB6G1RRPB6G1R[4:0]
RPB7RPB7G1RRPB7G1R[4:0]
RPB8RPB8G1RRPB8G1R[4:0]
RPB9RPB9G1RRPB9G1R[4:0]
Note:
  1. Denotes that these pins and their associated registers are not available in the 32-pin package.
Table 6-9. Remappable Output Pin Configuration – Group 2
RPn Port Pin RPnG2R SFR RPnG2R BitsRPnG2R Value to Peripheral Pin Selection
RPA0(1) RPA0G2R RPA0G2R [4:0]

00000 = OFF

00001 = SERCOM0_PAD0

00010 = SERCOM0_PAD3

00011 = SERCOM0_PAD2

00100 = OFF

00101 = SERCOM1_PAD3

00110 = SERCOM1_PAD2

00111 = TCC0_WO1

01000 = TCC0_WO5

01001 = TCC0_WO3

01010 = TCC1_WO1

01011 = TCC1_WO5

01100 = TCC1_WO3

01101 = TCC2_WO1

01110 = OFF

01111 = TC0_WO1

10000 = TC1_WO1

10001 = TC2_WO1

10010 = TC3_WO1

10011 = TC4_WO1

10100 = TC5_WO1

10101 = TC6_WO1

10110 = TC7_WO1

10111 = QSPI_CS

11000 = QSPI_DATA0

11001 = QSPI_DATA3

11010 = QSPI_DATA2

11011 = CCL_OUT1

11100 = Reserved

11101 = Reserved

11110 = Reserved

11111 = Reserved

RPA3RPA3G2RRPA3G2R[4.0]
RPA4RPA4G2RRPA4G2R[4.0]
RPA6RPA6G2RRPA6G2R[4.0]
RPA7RPA3G2RRPA7G2R[4.0]
RPA8RPA8G2RRPA8G2R[4.0]
RPB0(1)RPB0G2RRPB0G2R[4.0]
RPB1(1)RPB1G2RRPB1G2R[4.0]
RPB4RPB4G2RRPB4G2R[4.0]
RPB5RPB5G2RRPB5G2R[4.0]
RPB8RPB8G2RRPB8G2R[4.0]
RPB12(1)RPB12G2RRPB12G2R[4.0]
RPB13(1)RPB13G2R RPB13G2R[4.0]
Note:
  1. Denotes that these pins and their associated registers are not available in the 32-pin package.
Table 6-10. Remappable Output Pin Configuration - Group 3
RPn Port Pin RPnG3R SFR RPnG3R BitsRPnG3R Value to Peripheral Pin Selection
RPA0(1) RPA0G3R RPA0G3R [4:0]

00000 = OFF

00001 = OFF

00010 = SERCOM0_PAD0

00011 = SERCOM0_PAD3

00100 = SERCOM1_PAD2

00101 = OFF

00110 = SERCOM1_PAD3

00111 = TCC0_WO2

01000 = TCC0_WO0

01001 = TCC0_WO4

01010 = TCC1_WO2

01011 = TCC1_WO0

01100 = TCC1_WO4

01101 = TCC2_WO0

01110 = OFF

01111 = TC0_WO0

10000 = TC1_WO0

10001 = TC2_WO0

10010 = TC3_WO0

10011 = TC4_WO0

10100 = TC5_WO0

10101 = TC6_WO0

10110 = TC7_WO0

10111 = QSPI_CS

11000 = QSPI_DATA1

11001 = QSPI_DATA0

11010 = QSPI_DATA3

11011 = CCL_OUT0

11100 = Reserved

11101 = Reserved

11110 = Reserved

11111 = Reserved

RPA1(1)RPA1G3RRPA1G3R[4.0]
RPA3RPA3G3RRPA3G3R[4.0]
RPA4RPA4G3RRPA4G3R[4.0]
RPA5RPA5G3RRPA5G3R[4.0]
RPA8RPA8G3RRPA8G3R[4.0]
RPA9RPA9G3RRPA9G3R[4.0]
RPA13(1)RPA13G3RRPA13G3R[4.0]
RPB1(1)RPB1G3RRPB1G3R[4.0]
RPB2(1)RPB2G3RRPB2G3R[4.0]
RPB6RPB6G3RRPB6G3R[4.0]
RPB9RPB9G3RRPB9G3R[4.0]
RPB10(1)RPB10G3RRPB10G3R[4.0]
RPB13(1)RPB13G3R RPB13G3R[4.0]
Note:
  1. Denotes that these pins and their associated registers are not available in the 32-pin package.
Table 6-11. Remappable Output Pin Configuration – Group 4
RPn Port Pin RPnG4R SFR RPnG4R BitsRPnG4R Value to Peripheral Pin Selection
RPA1(1) RPA1G4R RPA1G4R[4:0]

00000 = OFF

00001 = SERCOM0_PAD2

00010 = OFF

00011 = SERCOM0_PAD0

00100 = SERCOM1_PAD3

00101 = OFF

00110 = SERCOM1_PAD0

00111 = TCC0_WO3

01000 = TCC0_WO1

01001 = TCC0_WO5

01010 = TCC1_WO3

01011 = TCC1_WO1

01100 = TCC1_WO5

01101 = TCC2_WO1

01110 = OFF

01111 = TC0_WO0

10000 = TC1_WO1

10001 = TC2_WO1

10010 = TC3_WO1

10011 = TC4_WO1

10100 = TC5_WO1

10101 = TC6_WO1

10110 = TC7_WO1

10111 = QSPI_CS

11000 = QSPI_DATA2

11001 = QSPI_DATA1

11010 = QSPI_DATA0

11011 = CCL_OUT1

11100 = Reserved

11101 = Reserved

11110 = Reserved

11111 = Reserved

RPA2(1)RPA2G4RRPA2G4R[4.0]
RPA4RPA4G4RRPA4G4R[4.0]
RPA5RPA5G4RRPA5G4R[4.0]
RPA6RPA6G4RRPA6G4R[4.0]
RPA8RPA8G4RRPA8G4R[4.0]
RPA9RPA9G4RRPA9G4R[4.0]
RPA10RPA10G4RRPA10G4R[4.0]
RPA13(1)RPA13G4RRPA13G4R[4.0]
RPA14(1)RPA14G4RRPA14G4R[4.0]
RPB2(1)RPB2G4RRPB2G4R[4.0]
RPB3(1)RPB3G4RRPB3G4R[4.0]
RPB7RPB7G4RRPB7G4R[4.0]
RPB10(1)RPB10G4RRPB10G4R[4.0]
RPB11(1)RPB11G4R RPB11G4R[4.0]
Note:
  1. Denotes that these pins and their associated registers are not available in the 32-pin package.