27.5.3 Clocks

The EIC bus clock (PB1_CLK) can be enabled and disabled by the CRU. The default state of PB1_CLK can be found in the CRU and PMD registers.

Some optional functions need a peripheral clock, which can either be a generic clock (GCLK_EIC, for wider frequency selection) or a Ultra Low-Power 32 KHz clock 32KHz_LPCLK, for the highest power efficiency). One of the clock sources must be configured and enabled before using the peripheral:

GCLK_EIC is configured and enabled in the CRU registers. For more details, see Clock and Reset Unit (CRU) from Related Links.

32KHz_LPCLK is provided by the various internal and external low power clock sources. For more details on configuration and selection of the clock, see Clock and Reset Unit (CRU) from Related Links.

Both GCLK_EIC and 32KHz_LPCLK are asynchronous to the user interface clock (PB1_CLK). Due to this asynchronicity, writes to certain registers require synchronization between the clock domains.