32.6.2.3.1 Synchronous Clock Operation
In Synchronous mode, the CTRLA.MODE bit field determines whether the transmission clock line (XCK) serves either as input or output. The dependency between clock edges, data sampling and data change is the same for internal and external clocks. Data input on the RxD pin is sampled at the opposite XCK clock edge when data is driven on the TxD pin.
- When CTRLA.CPOL is ‘
0
’, the data is changed on the rising edge of XCK and sampled on the falling edge of XCK. - When CTRLA.CPOL is ‘
1
’, the data is changed on the falling edge of XCK and sampled on the rising edge of XCK.
When the clock is provided through XCK (CTRLA.MODE = 0x0), the Shift registers operate directly on the XCK clock. This means that XCK is not synchronized with the system clock and, therefore, can operate at frequencies up to the system frequency.