9.2.2 Interrupt Line Mapping
The following table provides details about each of the interrupt lines that is connected to one peripheral instance. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.
An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by configuring it in the peripheral’s Interrupt Enable register.
An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled.
Depending on their criticality, the interrupt requests for one peripheral are either ORed together on system level, generating one interrupt, or directly connected to NVIC interrupt lines (see the following table).
An interrupt request sets the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).
For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.
Module | Source | NVIC Line |
---|---|---|
EIC NMI – External Interrupt Control | NMI | NMI |
RTCC – Real-Time Counter and Calendar | CMP A 0..3 | 0 |
OVF A | ||
PER A 0..7 | ||
TAMPER A | ||
EIC – External Interrupt Controller | EXTINT 0..3 | 1 |
FREQM – Frequency Meter | DONE | 2 |
FC – Flash Controller and PCHE | Flash Controller Program/erase complete | 3 |
PFW CRC Done | ||
PCACHE | ||
PORT-A | PortA Input Change Interrupt | 4 |
PORT-B | PortB Input Change Interrupt | 5 |
DMAC – Direct Memory Access Controller | SUSP 0..3 | 6 |
TCMPL 0..3 | ||
TERR 0..3 | ||
SUSP 4..15 | 7 | |
TCMPL 4..15 | ||
TERR 4..15 | ||
EVSYS – Event System Interface | EVD 0..3 | 8 |
OVR 0..3 | ||
EVD 4..11 | 9 | |
OVR 4..11 | ||
PAC – Peripheral Access Controller | ERR | 10 |
RAMECC - RAM Error Correction Code | SINGLEE-0 | 11 |
DualE-1 | ||
SERCOM0 – Serial Communication Interface 0(1) Order: USART, I2CM, I2CS, SPI | 0 | 12 |
1 | ||
2 | ||
3 | ||
4 | ||
5 | ||
7 | ||
SERCOM1 – Serial Communication Interface 1(1) Order: USART, I2CM, I2CS, SPI | 0 | 13 |
1 | ||
2 | ||
3 | ||
4 | ||
5 | ||
7 | ||
TCC0 – Timer Counter Control 0 | CNT A | 14 |
DFS A | ||
ERR A | ||
FAULTA A | ||
FAULTB A | ||
FAULT0 A | ||
FAULT1 A | ||
OVF | ||
TRG | ||
UFS A | ||
MC 0..5 | ||
TCC1 – Timer Counter Control 1 | CNT A | 15 |
DFS A | ||
ERR A | ||
FAULTA A | ||
FAULTB A | ||
FAULT0 A | ||
FAULT1 A | ||
OVF | ||
TRG | ||
UFS A | ||
MC 0..5 | ||
TCC2 – Timer Counter Control 2 | CNT A | 16 |
DFS A | ||
ERR A | ||
FAULTA A | ||
FAULTB A | ||
FAULT0 A | ||
FAULT1 A | ||
OVF | ||
TRG | ||
UFS A | ||
MC 0..1 | ||
TC0 – Basic Timer Counter 0 | ERR A | 17 |
MC 0 | ||
MC 1 | ||
OVF | ||
TC1 – Basic Timer Counter 1 | ERR A | 18 |
MC 0 | ||
MC 1 | ||
OVF | ||
TC2 – Basic Timer Counter 2 | ERR A | 19 |
MC 0 | ||
MC 1 | ||
OVF | ||
TC3 – Basic Timer Counter 3 | ERR A | 20 |
MC 0 | ||
MC 1 | ||
OVF | ||
TC4 – Basic Timer Counter 4 | ERR A | 21 |
MC 0 | ||
MC 1 | ||
OVF | ||
TC5 – Basic Timer Counter 5 | ERR A | 22 |
MC 0 | ||
MC 1 | ||
OVF | ||
TC6 – Basic Timer Counter 6 | ERR A | 23 |
MC 0 | ||
MC 1 | ||
OVF | ||
TC7 – Basic Timer Counter 7 | ERR A | 24 |
MC 0 | ||
MC 1 | ||
OVF | ||
ADC - Analog-to-Digital Converter | ADC_GIRQ | 25 |
ADC_DIRQ0, ADC_DIRQ1 | ||
ADC_AIRQ0, ADC_AIRQ1 | ||
ADC_FLT | 34 | |
ADC_FCC | 35 | |
ADC_BGVR_RDY | 36 | |
AC – Analog Comparators | COMP 0 | 26 |
COMP 1 | ||
WIN 0 | ||
CRYPTO | INT0 | 27 |
INT1 | 28 | |
INT2 | 41 | |
QSPI – Quad SPI interface | QSPI | 29 |
Wireless Subsystem (WZBT) | ZB_INT0 | 30 |
BT_INT0 | 31 | |
BT_INT1 | 32 | |
ARBITER | 33 | |
CLKI_WAKEUP_NMI | 37 | |
BT_LC | 42 | |
CVD - Capacitive Voltage Divider Controller | CVD | 38 |
SERCOM2 Serial Communication Interface 2(1) I2CM, I2CS | 0 1 2 3 4 5 6 7 | 40 |
Note:
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