9.2.2 Interrupt Line Mapping

The following table provides details about each of the interrupt lines that is connected to one peripheral instance. Each peripheral can have one or more interrupt flags, located in the peripheral’s Interrupt Flag Status and Clear (INTFLAG) register.

An interrupt flag is set when the interrupt condition occurs. Each interrupt in the peripheral can be individually enabled by configuring it in the peripheral’s Interrupt Enable register.

An interrupt request is generated from the peripheral when the interrupt flag is set and the corresponding interrupt is enabled.

Depending on their criticality, the interrupt requests for one peripheral are either ORed together on system level, generating one interrupt, or directly connected to NVIC interrupt lines (see the following table).

An interrupt request sets the corresponding interrupt pending bit in the NVIC interrupt pending registers (SETPEND/CLRPEND bits in ISPR/ICPR).

For the NVIC to activate the interrupt, it must be enabled in the NVIC interrupt enable register (SETENA/CLRENA bits in ISER/ICER). The NVIC interrupt priority registers IPR0-IPR7 provide a priority field for each interrupt.

Table 9-4. NVIC Interrupt Mapping
ModuleSourceNVIC Line
EIC NMI – External Interrupt ControlNMINMI
RTCC – Real-Time Counter and CalendarCMP A 0..30
OVF A
PER A 0..7
TAMPER A
EIC – External Interrupt ControllerEXTINT 0..31
FREQM – Frequency MeterDONE2
FC – Flash Controller and PCHEFlash Controller Program/erase complete3
PFW CRC Done
PCACHE
PORT-APortA Input Change Interrupt4
PORT-BPortB Input Change Interrupt5
DMAC – Direct Memory Access ControllerSUSP 0..36
TCMPL 0..3
TERR 0..3
SUSP 4..157
TCMPL 4..15
TERR 4..15
EVSYS – Event System InterfaceEVD 0..38
OVR 0..3
EVD 4..119
OVR 4..11
PAC – Peripheral Access ControllerERR10
RAMECC - RAM Error Correction CodeSINGLEE-011
DualE-1
SERCOM0 – Serial Communication Interface 0(1)

Order: USART, I2CM, I2CS, SPI

012
1
2
3
4
5
7
SERCOM1 – Serial Communication Interface 1(1)

Order: USART, I2CM, I2CS, SPI

013
1
2
3
4
5
7
TCC0 – Timer Counter Control 0CNT A14
DFS A
ERR A
FAULTA A
FAULTB A
FAULT0 A
FAULT1 A
OVF
TRG
UFS A
MC 0..5
TCC1 – Timer Counter Control 1CNT A15
DFS A
ERR A
FAULTA A
FAULTB A
FAULT0 A
FAULT1 A
OVF
TRG
UFS A
MC 0..5
TCC2 – Timer Counter Control 2CNT A16
DFS A
ERR A
FAULTA A
FAULTB A
FAULT0 A
FAULT1 A
OVF
TRG
UFS A
MC 0..1
TC0 – Basic Timer Counter 0ERR A17
MC 0
MC 1
OVF
TC1 – Basic Timer Counter 1ERR A18
MC 0
MC 1
OVF
TC2 – Basic Timer Counter 2ERR A19
MC 0
MC 1
OVF
TC3 – Basic Timer Counter 3ERR A20
MC 0
MC 1
OVF
TC4 – Basic Timer Counter 4ERR A21
MC 0
MC 1
OVF
TC5 – Basic Timer Counter 5ERR A22
MC 0
MC 1
OVF
TC6 – Basic Timer Counter 6ERR A23
MC 0
MC 1
OVF
TC7 – Basic Timer Counter 7ERR A24
MC 0
MC 1
OVF
ADC - Analog-to-Digital ConverterADC_GIRQ25
ADC_DIRQ0, ADC_DIRQ1
ADC_AIRQ0, ADC_AIRQ1
ADC_FLT34
ADC_FCC35
ADC_BGVR_RDY36
AC – Analog ComparatorsCOMP 026
COMP 1
WIN 0
CRYPTOINT027
INT128
INT241
QSPI – Quad SPI interfaceQSPI29
Wireless Subsystem (WZBT)ZB_INT030
BT_INT031
BT_INT132
ARBITER33
CLKI_WAKEUP_NMI 37
BT_LC42
CVD - Capacitive Voltage Divider ControllerCVD38
SERCOM2

Serial Communication Interface 2(1)

I2CM, I2CS

0

1

2

3

4

5

6

7

40
Note:
  1. The integer number specified in the source refers to the respective bit position in the INTFLAG register of the respective peripheral.