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26.2 Features
- Data Transfer From:
- Peripheral to peripheral
- Peripheral to memory
- Memory to peripheral
- Memory to memory
- Transfer Trigger Sources
- Software
- Events from event system
- Dedicated requests from peripherals
- SRAM-Based Transfer Descriptors
- Single transfer using one descriptor
- Multi-buffer or circular buffer modes by linking multiple descriptors
- Up to 16 Channels
- Enable 16 independent transfers
- Automatic descriptor fetch for each channel
- Suspend/resume operation support for each channel
- Flexible Arbitration Scheme
- Four configurable priority levels for each channel
- Fixed or round-robin priority scheme within each priority level
- From 1 to 256 KB Data Transfer in a Single Block Transfer
- Multiple Addressing Modes
- Static
- Configurable increment scheme
- Optional Interrupt Generation
- On block transfer complete
- On error detection
- On channel suspend
- Eight Event Inputs
- One event input for each of the eight least significant DMA channels
- Can be selected to trigger normal transfers, periodic transfers or conditional transfers
- Can be selected to suspend or resume channel operation
- Four Event Outputs
- One output event for each of the four least significant DMA channels
- Selectable generation on AHB, block or transaction transfer complete
- Error Management Supported by Write-Back Function
- Dedicated Write-Back memory section for each channel to store ongoing descriptor transfer
- CRC Polynomial Software Selectable to
- CRC-16 (CRC-CCITT)
- CRC-32 (IEEE 802.3)