33.6.4 DMA, Interrupts and Events
| Condition | Request | ||
|---|---|---|---|
| DMA | Interrupt | Event | |
| Data Register Empty (DRE) | Yes (request cleared when data are written) | Yes | NA |
| Receive Complete (RXC) | Yes (request cleared when data are read) | Yes | |
| Transmit Complete (TXC) | NA | Yes | |
| SPI Select Low (SSL) | NA | Yes | |
| Error (ERROR) | NA | Yes | |
| Condition | Request | ||
|---|---|---|---|
| DMA | Interrupt | Event | |
Standard (DRE) – Data Register Empty FIFO (DRE) – at least TXTRHOLD locations in TX FIFO are empty | Yes (request cleared when data are written) | Yes | NA |
Standard (RXC) – Receive Complete FIFO (RXC) – at least RXTRHOLD data available in RX FIFO, or a last word available and length frame reception completed. | Yes (request cleared when data are read) | Yes | |
Standard (TXC) – Transmit Complete FIFO (TXC) – Transmit Complete and TX FIFO is empty | NA | Yes | |
| SPI Select Low (SSL) | NA | Yes | |
| Error (ERROR) | NA | Yes | |