4 FPGA Programming Circuitry

The underlying device programming circuitry is implemented by a dedicated programming bus. This parallel bus implements address, data and control bus parity, preventing incorrect write cycles in the event of SEU. Also, all critical configuration registers are TMR protected. When unused, this bus is held in asynchronous reset for further SEU protection.

Any SEU's in programming circuitry are covered, by default, in Microchip SEU reports, which show overall SEU rates at levels acceptable or better for aviation applications.