3.2 SmartDebug Radiation Exposure and Mitigation

The underlying SmartDebug circuitry is implemented primarily by ASIC logic. The exception being the Fabric Hardware Breakpoints, which are implemented as FPGA fabric logic. The ASIC logic is asynchronous logic with some amount of synchronous logic. Adhering to the recommendations provided, it holds the majority of synchronous logic in reset, minimizing any deleterious effects due to SEE for safety-critical applications. The remaining asynchronous logic would require multiple SEE events to result in unwanted SmartDebug access. This is due to the bus style architecture required to access these circuits.

To minimize the impact of SEE exposure, it is recommended to disable and/or minimize the SmartDebug circuitry as follows:
  1. Enable the System Controller suspend mode. In this configuration, the System Controller is driven into TMR'd asynchronous reset. In this state, the controller cannot initiate access to the SmartDebug circuity due to an SEE event. In this mode, the System Controller reset output holds the SmartDebug logic in reset.
  2. Disable the Fabric Hardware Breakpoints (FHB). This removes the circuitry from the FPGA fabric, reducing SEE footprint of the design proportionally.
  3. Reserve the two available Live Probe pins and do not use them as user I/O.

Any SEU's in SmartDebug circuitry are covered, by default, in Microchip SEU reports, which show overall SEU rates at levels acceptable or better for aviation applications.