2.2 Design Description

The 10GBASE-R Ethernet SyncE loopback simulation design includes the following components:

Testbench_10g: Top testbench module that generates the clocks required for the device under test (DUT) and the testbench submodule, and interconnects the ports from DUT to the testbench submodule.
top_tb: Testbench submodule, which consists of the following major blocks:
- CoreABC: Configures 10G MAC registers.
- packet_generator_checker: Performs the packet generator function of defining the Ethernet frame to be transmitted to CORE10GMAC (packet generator). Performs the packet checker function of receiving the looped back Ethernet frame from the CORE10GMAC and comparing it with the transmitted frame.
- CORE10GMAC: 10 Gbps Ethernet MAC configured in Base-R mode that transmits and receives the Ethernet packets.
top: DUT block of the design, which consists of the following major blocks:
- CORE10GMAC: 10 Gbps Ethernet MAC configured in Base-R mode that transmits and receives the Ethernet packets.
- Transceiver: 10GBASE-R physical interface for data transfers; configured in 64b/66b mode with a PCS fabric width of 64 bits.
- CoreABC: Configures the CORE10GMAC registers.
- FIFO interface logic: Loops back the Ethernet packets, implemented in Verilog RTL. The following table lists the simulation signals transmitted between the Testbench_10g, top, and top_tb blocks.

Table 2-1. Simulation Signals
Output From	Input To	Signal	Description
testbench_10g	top, top_tb	SYSCLK	156.25 MHz clock
testbench_10g	top, top_tb	OUT0_FABCLK_0_net_0	50 MHz clock
top	testbench_10g	LANE0_RXD_P	Rx port signals
		LANE0_RXD_N	Rx port signals
		LANE0_TXD_P	Tx port signals
		LANE0_TXD_N	Tx port signals
top_tb	testbench_10g	LANE0_RXD_P_0	Rx port signals
		LANE0_RXD_N_0	Rx port signals
		LANE0_TXD_P_0	Tx port signals
		LANE0_TXD_N_0	Tx port signals

AN5102