1 Demo Design
(Ask a Question)The 10GBASE-R Ethernet SyncE loopback hardware design loops back the Ethernet traffic generated by Optical Network Tester (ONT) through the CORE10GMAC IP. A FIFO logic is implemented in the RTL to loop the RX signals of the Core10G MAC back to the TX signals of the MAC.
This looped back data is sent through the TX interface of the transceiver that is received by ONT. Using the ONT software, the received data is analyzed for throughput rate and errors in the incoming packets and ppm difference.
The 10GBASE-R Ethernet SyncE loopback design includes the following components:
- CORE10GMAC: Serves as a 10 Gbps Ethernet MAC that transmits and receives the Ethernet packets.
- Transceiver: Acts as a 10GBASE-R physical interface for data transfers; configured for 64b/66b encoding/decoding with scrambler/descrambler enabled with a PCS interface width of 32 bits to the CORE10GMAC and JAPLL option enabled.
- CoreABC: Configures the CORE10GMAC registers.
- FIFO Interface Logic: Loops back the CORE10GMAC Rx data to Tx data.
- PF_TX_PLL: Generates the bit clock required for the transceiver and the clock option is set to Jitter cleaning mode to enable the Jitter attenuator PLL.
- PF_XCVR_REF_CLK: Generates the fabric clock and the reference clock for the transceiver and the TX_PLL.
The following table lists the clock frequencies used in the design.
| Clock | Frequency (MHz) |
|---|---|
| CDR reference clock | 156.25 |
| Transceiver bit clock | 5156.25 |
| I_SYS_CLOCK | 156.25 |
| I_CORE_TX_CLK | 322.26 |
| I_CORE_RX_CLK | 322.26 |
| JA_REF_CLK | 322.26 |
| PCLK | 50 |
The following figure shows the top-level block diagram of the PolarFire 10G Base-R Ethernet SyncE loopback hardware implementation.
