4 Running the Demo

Follow these steps to run the PolarFire 10GBASE-R Ethernet SyncE loopback hardware demo design on the PolarFire Evaluation Board.

  1. The reference design is validated using ONT. There exists the ppm offset in the TX and RX frequencies when the Jitter Cleaning Mode is not enabled in the TX PLL as shown in the following figure.
    Figure 4-1. Frequency Offset—SyncE Disabled
  2. When the design is built with Jitter Cleaning Mode of TX PLL enabled the Frequency offset between TX and RX is 0 ppm.
    Figure 4-2. Frequency Offset Between TX and RX
  3. When the TX clock frequency is offset by 100 ppm, the RX clock frequency also gets adjusted by 100 ppm, which shows that JA PLL is tracking and adjusting the clock as per the offset in the received clock.
  4. The data generated by the ONT tester is looped back at the FIFO and received at the ONT tester. The data throughput is verified and displayed on the ONT screen by the All Layers OK indicator in green color, as shown in the following figure.
    Figure 4-3. Frequency Offset—SyncE Enabled