14.6.7 Fault Injection Control Register
Note:
- Writes to any registers while SYNCBUSY.SWRST is asserted will produce a bus error.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | FLTCTRL |
| Offset: | 0x0018 |
| Reset: | 0x00000000 |
| Property: | PAC Write Protection |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| Access | |||||||||
| Reset |
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| FLTMD[1:0] | |||||||||
| Access | R/W | R/W | |||||||
| Reset | 0 | 0 | |||||||
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLTEN | |||||||||
| Access | R/W | ||||||||
| Reset | 0 |
Bits 13:12 – FLTMD[1:0] Fault Mode Control
Note: The Fault Address is defined by the IFLTADR register for the ITCM and the
DFLTADR register for DTCMs.
| Value | Description |
|---|---|
| 00 | Fault Injection Disabled |
| 01 | Single Fault Injection (at bit selected by FLT1PTR) for Writes |
| 10 | Double Fault Injection (at bits selected by FLT1PTR and FLT2PTR) for Writes |
| 11 | Reserved |
Bit 1 – FLTEN Fault Injection Enabled
Note: Faults will be injected for ITCM and DTCMs and the results captured in the
corresponding registers.
| Value | Description |
|---|---|
| 0 | Disables the fault injection. |
| 1 | Enables the fault injection selected by FLTMD. |