14.6.8 ITCM Fault Injection Pointer Register
Note:
- Writes to any registers while SYNCBUSY.SWRST is asserted will produce a bus error.
| Symbol | Description | Symbol | Description | Symbol | Description |
|---|---|---|---|---|---|
| R | Readable bit | HC | Cleared by Hardware | (Grey cell) | Unimplemented |
| W | Writable bit | HS | Set by Hardware | X | Bit is unknown at Reset |
| K | Write to clear | S | Software settable bit | — | — |
| Name: | IFLTPTR |
| Offset: | 0x001C |
| Reset: | 0x00000000 |
| Property: | PAC Write Protection, Enable-Protected |
| Bit | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | |
| Access | |||||||||
| Reset |
| Bit | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | |
| FLT2PTR[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
| Bit | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | |
| Access | |||||||||
| Reset |
| Bit | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | |
| FLT1PTR[6:0] | |||||||||
| Access | R/W | R/W | R/W | R/W | R/W | R/W | R/W | ||
| Reset | 0 | 0 | 0 | 0 | 0 | 0 | 0 | ||
Bits 22:16 – FLT2PTR[6:0] ECC Fault injection Bit position pointer (for double bit error)
0000000 = Fault injection (bit inversion) occurs on bit 0 of ECC bit order
0000001 = Fault injection (bit inversion) occurs on bit 1 of ECC bit order
*
*
1000111= Fault injection (bit inversion) occurs on bit 71 of ECC bit order
1001000 to 1111111 = No fault injection occurs for bit positions 72-127
Bits 6:0 – FLT1PTR[6:0] ECC Fault injection Bit position pointer (for single/double bit error)
0000000 = Fault injection (bit inversion) occurs on bit 0 of ECC bit order
0000001 = Fault injection (bit inversion) occurs on bit 1 of ECC bit order
*
*
1000111= Fault injection (bit inversion) occurs on bit 71 of ECC bit order
1001000 to 1111111 = No fault injection occurs for bit positions 72-127